Hardware Implementation of Fano Decoder for PAC Codes

This paper proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture maintains a trade-off between the error-correction performance and throughput of the decoder by setting a strict limit on its search complexity. The paper presents analyses of the complexity, combinational delay, and latency of the proposed architecture. The performance of the proposed decoder is evaluated on FPGA and ASIC using Xilinx Nexys 4 Artix-7 and TSMC 28 nm 0.72 V library, respectively. The PAC decoder can be clocked at 384.6 MHz and reach an information throughput of 9.34 MB/s at 3.5 dB signal-to-noise ratio for a block length of 128 and code rate of 1/2.