2CIM: Area-Efficient 2-Cycle Integer Multipliers

Fast multipliers with large bit widths can occupy significant silicon area, which, in turn, can be minimized by employing multi-cycle multipliers. This paper introduces architectures and parameterized Verilog circuit generators for 2-cycle integer multipliers. When implementing an algorithm in hardware, it is common that less than 1 multiplication needs to be performed per clock cycle. It is also possible that the multiplications per cycle is a fractional number, e.g., 3.5. In such case, we can surely use 4 multipliers, each with a throughput of 1 result per cycle. However, we can instead use 3 such multipliers plus a multiplier with a throughput of 1/2. Resource sharing allows a multiplier with a lower throughput to be smaller, hence area savings. These multipliers offer customization in regards to the latency and clock frequency. All proposed designs were automatically synthesized and tested for various bit widths. Two main architectures are presented in this work, and each has several variants. Our 2-cycle multipliers offer up to 21%, 42%, 32%, 41%, and 48% of area savings for bit widths of 8, 16, 32, 64, and 128, with respect to synthesizing the "*" operator with throughput of 1. Furthermore, some of the proposed designs also offer power savings under certain conditions.