This paper presents a design space exploration for SABER, one of the finalists in NIST's quantum-resistant public-key cryptographic standardization effort. Our design space exploration targets a 65nm ASIC platform and has resulted in the evaluation of 6 different architectures. Our exploration is initiated by setting a baseline architecture which is ported from FPGA. In order to improve the clock frequency (the primary goal in our exploration), we have employed several optimizations: (i) use of compiled memories in a 'smart synthesis' fashion, (ii) pipelining, and (iii) logic sharing between SABER building blocks. The most optimized architecture utilizes four register files, achieves a remarkable clock frequency of 1GHz while only requiring an area of 0.314mm2. Moreover, physical synthesis is carried out for this architecture and a tapeout-ready layout is presented. The estimated dynamic power consumption of the high-frequency architecture is approximately 184mW for key generation and 187mW for encapsulation or decapsulation operations. These results strongly suggest that our optimized accelerator architecture is well suited for high-speed cryptographic applications.
翻译:本文介绍了国家科学研究所量子抗衡公用钥匙标准化努力的决赛者之一SABER的设计空间探索。我们的设计空间探索的目标是一个65nm ASIC平台,并导致对6个不同的建筑进行了评价。我们的探索是通过建立一个从FPGA移植的基线结构而开始的。为了改进时钟频率(我们勘探的首要目标),我们采用了几种优化方法:(一) 以“智能合成”方式使用汇编的记忆,(二) 管道,和(三) SABER建筑块之间的逻辑共享。最优化的建筑使用4个登记文件,达到1GHz的惊人时钟频率,而仅需要0.314毫米的面积。此外,还对这一建筑进行了物理合成,并展示了一种可粘贴的布局。估计高频结构的动力消耗量大约为184mW用于关键生成,187mW用于封装或卸载操作。这些结果有力地表明,我们最优化的加速加速的加密结构非常适合高速加密应用。