Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of $1.48$ Gbps is achieved with a bit error rate (BER) of $10^{-5}$ at around $E_b/N_0 = - 0.40$ dB. The decoder can also achieve the same BER at $E_b/N_0 = - 1.11$ dB with a reduced throughput of $0.20$ Gbps.
翻译:Hadamard 低密度电码(PLDPC-HCs)是一种新型的终极Shannon限制法代码。 在本文中, 我们为 PLDPC- HC 层解码器建议了一个硬件结构。 解码器主要由随机地址记忆、 Hadamard 子解码器和控制逻辑组成。 展示了两种管道结构,并得出了这两个结构的延时和吞量。 在FPGA 板上实施解码器设计表明, 以10美元至5美元的略误率( BER) 达到1.48美元Gbps的通过量, 大约为 $_b/N_0 = - 0. 40 dB。 解码器还可以以$_b/N_0 = 1.11美元达到相同的ERB, 减少0.20 Gbps的通过量。