Vast requirement of computation power of Deep Neural Networks is a major hurdle to their real world applications. Many recent Application Specific Integrated Circuit (ASIC) chips feature dedicated hardware support for Neural Network Acceleration. However, as ASICs take multiple years to develop, they are inevitably out-paced by the latest development in Neural Architecture Research. For example, Transformer Networks do not have native support on many popular chips, and hence are difficult to deploy. In this paper, we propose Arch-Net, a family of Neural Networks made up of only operators efficiently supported across most architectures of ASICs. When a Arch-Net is produced, less common network constructs, like Layer Normalization and Embedding Layers, are eliminated in a progressive manner through label-free Blockwise Model Distillation, while performing sub-eight bit quantization at the same time to maximize performance. Empirical results on machine translation and image classification tasks confirm that we can transform latest developed Neural Architectures into fast running and as-accurate Arch-Net, ready for deployment on multiple mass-produced ASIC chips. The code will be available at https://github.com/megvii-research/Arch-Net.
翻译:深神经网络的广大计算能力要求是其真实世界应用的一大障碍。 最近许多应用特定集成电路芯片(ASIC)芯片的功能是神经网络加速的专用硬件支持。 然而,随着ASIC的开发需要多年时间,它们不可避免地被神经结构研究的最新开发速度所超过。例如,变压器网络对许多受欢迎的芯片没有本地的支持,因此难以部署。在本文中,我们提议由神经网络组成的一个网络大家庭,它由大多数ASIC结构中高效支持的操作者组成。当Arch-Net产生时,通过无标签的封闭式模型蒸馏,逐渐消除不太普通的网络结构,如层的正常化和嵌入层,同时进行小八位四分位化,以最大限度地提高性能。关于机器翻译和图像分类任务的实际结果证实,我们可以将最新开发的神经结构转换为快速运行和同步的Arch-Net-Net,准备在多个大规模生产的ASICTIEC芯片上部署。该代码将在 https://greath/searge-Ang-rebub.com上提供。