The increasing transistor scale integration poses, among others, the thermal-aware floorplanning problem; consisting of how to place the hardware components in order to reduce overheating by dissipation. Due to the huge amount of feasible floorplans, most of the solutions found in the literature include an evolutionary algorithm for, either partially or completely, carrying out the task of floorplanning. Evolutionary algorithms usually have a bottleneck in the fitness evaluation. In the problem of thermal-aware floorplanning, the layout evaluation by the thermal model takes 99.5\% of the computational time for the best floorplanning algorithm proposed so far.The contribution of this paper is to present a parallelization of this evaluation phase in a master$-$worker model to achieve a dramatic speed-up of the thermal-aware floorplanning process. Exhaustive experimentation was done over three dimensional integrated circuits, with 48 and 128 cores, outperforming previous published works.
翻译:晶体管规模的日益整合,除其他外,除其他外,带来了热能地面规划问题;包括如何放置硬件组件,以减少因消散而过热的情况;由于大量可行的地面规划,文献中发现的大多数解决办法包括部分或完全执行地面规划任务的演进算法;进化算法通常在健身评估中有一个瓶颈;在热能地面规划问题中,热能模型的布局评价需要99.5 % 的计算时间来计算迄今提出的最佳地面规划算法。</s>