Testing an integrated circuit (IC) is a highly compute-intensive process. For today's complex designs, tests for many hard-to-detect faults are typically generated using deterministic test generation (DTG) algorithms. Machine Learning (ML) is being increasingly used to increase the test coverage and decrease the overall testing time. Such proposals primarily reduce the wasted work in the classic Path Oriented Decision Making (PODEM) algorithm without compromising on the test quality. With variants of PODEM, many times there is a need to backtrack because further progress cannot be made. There is thus a need to predict the best strategy at different points in the execution of the algorithm. The novel contribution of this paper is a 2-level predictor: the top level is a meta predictor that chooses one of several predictors at the lower level. We choose the best predictor given a circuit and a target net. The accuracy of the top-level meta predictor was found to be 99\%. This leads to a significantly reduced number of backtracking decisions compared to state-of-the-art ML-based and conventional solutions. As compared to a popular, state-of-the-art commercial ATPG tool, our 2-level predictor (HybMT) shows an overall reduction of 32.6\% in the CPU time without compromising on the fault coverage for the EPFL benchmark circuits. HybMT also shows a speedup of 24.4\% and 95.5\% over the existing state-of-the-art (the baseline) while obtaining equal or better fault coverage for the ISCAS'85 and EPFL benchmark circuits, respectively.
翻译:集成电路的测试是一个高度计算密集型的过程。对于现今的复杂设计,往往使用确定性测试生成(DTG)算法来生成许多难以检测的故障测试。机器学习(ML)被越来越多地用于增加测试覆盖率并减少总测试时间。这样的提案主要是减少经典路径导向决策(PODEM)算法中的浪费工作,同时不损害测试质量。但是,针对PODEM的变体,很多时候需要回溯,因为无法进一步进行。因此,在算法执行的不同点上需要预测最佳策略。本文的创新贡献是一个两级预测器:顶层是一个元预测器,在低层中选择几个预测器之一。我们选择最好的预测器,给定电路和目标网。顶级元预测器的准确度达到了99\%。与现有的最先进的基于ML和传统解决方案相比,这导致了显著减少的回溯决策数量。与流行的、现有的最先进的商用ATPG工具相比,我们的两级预测器(HybMT)显示出CPU时间总体减少了32.6%,而不损害EPFL基准电路的故障覆盖率。在ISCAS'85和EPFL基准电路中,HybMT在获得相等或更好的故障覆盖率的情况下显示出比现有最先进工具(基线)更快的速度提升24.4%和95.5%。