Formal specification is a basis for rigorous software implementation. VDM-SL is a formal specification language with an extensive executable subset. Successful cases of VDM-family including VDM-SL have shown that producing a well-tested executable specification can reduce the cost of the implementation phase. This paper introduces and discusses the reversed order of specification and implementation. The development of a multi-agent simulation language called \remobidyc is described and examined as a case study of defining a formal specification after initial implementation and reflecting the specification into the implementation code.
翻译:正式规范是严谨软件实现的基础。 VDM-SL是一种具有广泛可执行子集的正式规范语言。 VDM-family的成功案例包括VDM-SL,已经表明制作经过良好测试的可执行规范可以减少实现阶段的成本。本文介绍和讨论了规范和实现的反向顺序。描述和检查了开发一个称为“remobidyc”的多智能体模拟语言作为定义初始实现之后的正式规范的案例研究,并将规范反映到实现代码中。