The increasing growth of applications' memory capacity and performance demands has led the CPU vendors to deploy heterogeneous memory systems either within a single system or via disaggregation. For instance, systems like Intel's Knights Landing and Sapphire Rapids can be configured to use high bandwidth memory as a cache to main memory. While there is significant research investigating the designs of DRAM caches, there has been little research investigating DRAM caches from a full system point of view, because there is not a suitable model available to the community to accurately study largescale systems with DRAM caches at a cycle-level. In this work we describe a new cycle-level DRAM cache model in the gem5 simulator which can be used for heterogeneous and disaggregated systems. We believe this model enables the community to perform a design space exploration for future generation of memory systems supporting DRAM caches.
翻译:应用程序的内存容量和性能需求的不断增长,已经促使CPU供应商通过单一系统内或通过分离部署异构存储器系统。例如,Intel的 Knights Landing 和 Sapphire Rapids 系统可以配置为使用高带宽内存作为主存的缓存。虽然存在大量研究来研究DRAM缓存的设计,但是从整个系统的角度研究DRAM缓存的研究很少,因为目前没有合适的模型能够准确地以周期级别来研究带有DRAM缓存的大规模系统。在本研究工作中,我们在gem5模拟器中描述了一种新的周期级别的DRAM缓存模型,该模型可用于异构和分离的系统。我们认为,这种模型可以使社区对支持DRAM缓存的下一代存储系统进行设计空间的探索。