纳米工艺下面向参数成品率增强的电路设计方法研究

项目名称： 纳米工艺下面向参数成品率增强的电路设计方法研究

项目编号： No.61274035

项目类型： 面上项目

立项/批准年度： 2013

项目学科： 无线电电子学、电信技术

项目作者： 韩雁

作者单位： 浙江大学

项目金额： 80万元

中文摘要： 高端高性能IC设计制造中，工艺离散、电源波动和温度变化(PVT)都会严重影响IC性能参数成品率。本项目综合考虑PVT变化因素，通过建模形成一套在纳米工艺下对MOS管阈值电压准确预测的方法。基于此模型，提出一种面向参数成品率增强的片上体偏置技术，该技术用一种自主创新的自动反馈型电路设计方法补偿模拟/数模混合，尤其是低压低功耗亚阈值IC在制造过程中PVT涨落带来的不利影响，并最终形成了一套在纳米先进工艺下抗PVT涨落影响的设计理论和方法。为了验证该方法的有效性，本项目将其应用到可在极低功耗模拟信号放大电路中使用的C类反相器中，解决了由于该C类反相器的亚阈值工作状态而对PVT相当敏感的问题；为了验证该方法在较大规模高端IC中的实用性，本项目还计划将其应用到极低功耗高性能音频ADC的设计实现中。基于65nm或40nm CMOS工艺，预期ADC综合指标FOM达到0.6pJ/step的国际先进水平。

中文关键词： 纳米工艺；抗工艺涨落；参数成品率；片上体偏置；

英文摘要： In high-end high-performance IC design and manufacture, process, supply voltage and temperature (PVT) variations seriously affect the IC parametric yield. This project aims to consider the PVT-variation factors by modeling and then provide an accurate prediction method for the threshold voltage of MOS transistors in nanometer technology. Based on this model, an on-chip body bias technique for the enhancement of parametric yield is proposed. This technique adopts an innovative "automatic feedback" circuit design methodology to compensate for PVT-variations in analog/mixed-signal IC, especially in low-voltage low-power sub-threshold IC, and ultimately forms a set of design theory and methodology for reducing PVT-variations in advanced nanometer technology. To verify the effectiveness of the methodology, this project applies it to a class-C inverter which is used in low-power analog signal amplification, solving the problem that the traditional class-C inverter is sensitive to PVT-variations because of its subthreshold status; to verify the practicality of the methodology in large-scale high-end IC, this project also plans to apply it to ultra-low-power high-performance audio ADC. Based on 65-nm or 40-nm CMOS technology, the FOM specification of the proposed ADC is expected to be 0.6pJ/step, reaching international

英文关键词： nanometer process；resist PVT variation；parametric yield；on-chip body bias；