Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. Since integrated circuits (ICs) can naturally be represented as graphs, there has been a tremendous surge in employing GNNs for machine learning (ML)-based methods for various aspects of IC design. Given this trajectory, there is a timely need to review and discuss some powerful and versatile GNN approaches for advancing IC design. In this paper, we propose a generic pipeline for tailoring GNN models toward solving challenging problems for IC design. We outline promising options for each pipeline element, and we discuss selected and promising works, like leveraging GNNs to break SOTA logic obfuscation. Our comprehensive overview of GNNs frameworks covers (i) electronic design automation (EDA) and IC design in general, (ii) design of reliable ICs, and (iii) design as well as analysis of secure ICs. We provide our overview and related resources also in the GNN4IC hub at https://github.com/DfX-NYUAD/GNN4IC. Finally, we discuss interesting open problems for future research.
翻译:由于集成电路(ICS)自然可以作为图解来表示,因此在采用基于GNNS的机器学习方法来进行ICS设计的各个方面,在采用基于GNS的机械学习方法方面出现了巨大增长。鉴于这一轨迹,及时需要审查和讨论一些推动ICS设计的强大和多才多艺的GNN方法。在本文件中,我们提议了一种通用管道,用于调整GNN模式,以解决IC设计中具有挑战性的问题。我们概述了每个管道要素的有希望的选择,我们讨论了选定和有希望的工程,例如利用GNNS打破SOTA逻辑模糊。我们对GNNS框架的全面概述包括:(一) 电子设计自动化(EDA) 和IC总体设计,(二) 设计可靠的ICS,以及(三) 设计和分析安全的ICS。我们还在https://github.com/DNU中心提供我们概览和相关资源,供我们讨论GNNN4N4CF.G.LU.