ALEGO: Towards Cost-Aware Architecture and Integration Co-Design for Chiplet-based Spatial Accelerators

Advanced packaging offers a new design paradigm in the post-Moore era, where many smaller chiplets could be assembled into a large system to achieve extreme scalability and cost reduction. Recently proposed chiplet-based DNN accelerators demonstrate its effectiveness but fail to explore the tradeoffs between PPA and the fabrication cost. Specifically, we should explore both the architectural design space for individual chiplets and different integration options to assemble these chiplets. More advanced (and costly) packaging technology can enhance connectivity, but may meanwhile reduce the budget on chiplets. In this paper, we propose ALEGO, an architecture-and-integration co-design approach for chiplet-based spatial accelerators. Based on a heterogeneous integration paradigm, ALEGO can optimize each chiplet design for different workloads to achieve better efficiency. The co-design is enabled by using uniform architecture and integration encoding and a systematic design space exploration flow. We develop an architecture modeling framework and an ML-based approach to optimize the design parameters. Experiments demonstrate that ALEGO achieves 24%, 16%, or 23% improvement in latency, energy, and cost, respectively compared with the best of separate architecture or integration optimization.