Chips with hundreds to thousands of cores require scalable networks-on-chip (NoCs). Customization of the NoC topology is necessary to reach the diverse design goals of different chips. We introduce sparse Hamming graph, a novel NoC topology with an adjustable costperformance trade-off that is based on four NoC topology design principles we identified. To efficiently customize this topology, we develop a toolchain that leverages approximate floorplanning and link routing to deliver fast and accurate cost and performance predictions. We demonstrate how to use our methodology to achieve desired cost-performance trade-offs while outperforming established topologies in cost, performance, or both.
翻译:具有数十万至数千个核心芯片的芯片需要可扩缩的芯片网络(NOCs ) 。 要实现不同芯片的不同设计目标,就必须对NoC的地形进行定制。 我们引入了稀疏的Hamming图,这是一个新颖的NoC的地形图,根据我们确定的4个NoC的地形设计原则进行可调整的成本绩效权衡。为了高效定制这一地形图,我们开发了一个工具链,利用大约的地板规划以及连接路径来提供快速和准确的成本和性能预测。我们展示了如何使用我们的方法实现预期的成本绩效交易,同时在成本、性能或两者上都优于既定的地形。