Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems

Current design-space exploration tools cannot accurately evaluate communication-intensive applications whose execution is data-dependent (e.g., graph analytics and sparse linear algebra) on scale-out manycore systems, due to either lack of scalability or lack of detail in modeling the network. This paper presents Muchisim, a novel parallel simulator designed to address the challenges in exploring the design space of distributed multi-chiplet manycore architectures for communication-intensive applications. We evaluate Muchisim at simulating systems with up to a million interconnected processing elements (PEs) while modeling data movement and communication in a cycle-accurate manner. In addition to performance, Muchisim reports the energy, area, and cost of the simulated system, and it comes with a benchmark application suite and two data visualization tools. Muchisim supports various parallelization strategies and communication primitives such as task-based parallelization and message passing, making it highly relevant for architectures with software-managed coherence and distributed memory. Via a case study, we show that Muchisim helps users explore the balance between memory and computation units and the constraints related to chiplet integration and inter-chip communication. Muchisim enables scaling up the systems in which new techniques or design parameters are evaluated, opening the gate for further research in this area.