FPGA-extended Modified Harvard Architecture

This paper introduces a computer architecture, where part of the instruction set architecture (ISA) is implemented on small highly-integrated field-programmable gate arrays (FPGAs). It has already been demonstrated that small FPGAs inside a general-purpose processor (CPU) can be used effectively to implement custom instructions and, in some cases, approach accelerator-level of performance. Our proposed architecture goes one step further to directly address some related challenges for high-end CPUs, where such highly-integrated FPGAs would have the highest impact, including access to the memory hierarchy with the highest bandwidth available. The main contribution is the introduction of the "FPGA-extended modified Harvard architecture" model to enable software-transparent context-switching between processes with a different distribution of instructions. The simulation-based evaluation of a dynamically reconfigurable core shows promising results for single and multi-processing, approaching the performance of an equivalent core with all enabled instructions, and better performance than when featuring a fixed subset of the supported instructions. Finally, the feasibility of adopting the proposed architecture in today's CPUs is studied through the prototyping of fast-reconfigurable FPGAs and studying the miss behaviour of opcodes.