众核处理器中能效驱动的存储和互连网络系统研究

项目名称： 众核处理器中能效驱动的存储和互连网络系统研究

项目编号： No.61303069

项目类型： 青年科学基金项目

立项/批准年度： 2014

项目学科： 自动化技术、计算机技术

项目作者： 周宏伟

作者单位： 中国人民解放军国防科学技术大学

项目金额： 23万元

中文摘要： 功耗已成为制约高性能计算系统性能提升的主要壁垒，提高微处理器的能效是设计高性能计算系统的关键。随着芯片规模增大，数据在片上存储和互连网络中的移动能耗显著增加，成为众核处理器设计遇到的新障碍。本项目面向下一代64~128核心的众核处理器，提出一种能效驱动的紧耦合可扩展片上存储和互连网络体系结构（ecsMNA），实现处理器核与存储和互连系统的平衡、协同数据移动的高能效。主要研究内容有：（1）有限能量预算的CPU芯片总体架构，如何对计算、存储和互连网络资源进行最优分配。（2）ecsMNA总体结构及关键技术，包括能效驱动的片上数据移动机制、数据局部化优化策略、可扩展的多级互连网络等。（3）性能和功耗模拟器设计，构造整合片上存储、网络和一致性协议的性能和功耗模型，支持多指标模拟和自动优化。本项目的研究成果将为面向高性能计算系统的下一代CPU的研制做准备，对提高国产CPU体系结构设计水平具有重要意义。

中文关键词： 众核处理器；能效；存储；互连；网络

英文摘要： Power has become a main bottleneck for the improvement of high-performance computing system's performance. Energy efficiency is very important for the future high-performance computing systems. With the chip size enlarges, energy consumed by data moving in memory hierarchies and on-chip network is more obvious, it becomes a new obstacle for many-core processor design. For next generation many-core processor with 64~128 cores, we proposed an energy-efficiency-driven close-coupling scalable Memory and Network Architecture(ecsMNA) to realize the balance of transistor resources among cores, memory and interconnects, to acquire a high energy-efficiency of orchestrating data moving in memory hierarchies and interconnects. Main researches include the following: Firstly, how to design a holistic CPU architecture under the limits of energy budget. Best allocation of the transistor resources among cores, memory and interconnects is the key problem to be resolved. Secondly, the framework of ecsMNA is proposed and correlative key technologies that include energy-efficiency-driven data moving mechanism, data locality optimization policies and scalable multi-level network designs will be researched. Finally, processor simulator will be designed. A performance and power combined model is built which considers memory hierarchie

英文关键词： many-core processor；energy-efficiency；memory；interconnect；network