3D FPGAs have recently been produced as the next generation of the FPGA family to continue the integration of more transistors on a single chip seamlessly. In this paper, we propose a complete CAD flow to implement an arbitrary logic circuit on the 3D FPGA. The partitioning and placement stages of the flow are based on the simulated annealing algorithm. Furthermore, the routing stage is a modified version of the Pathfinder algorithm. The simulation results indicate that the comparison between 2D FPGA and 3D FPGA (including 2-tier) shows that the circuit speed increases by 28.66% and minimum channel width decrease by 29.92%, while the total area raises by 8.86%. Finally, the results of the comparison between 2-tier and 4-tier in 3D FPGA show that circuit speed and minimum channel width increase by 15.95% and 15.92% in 4-tier, respectively. Meanwhile, the total area increases only by 1.96%.
翻译：近年来，3D FPGA 作为 FPGA 家族的下一代产品已经问世，以便于在单个芯片上无缝集成更多晶体管。本文提出了一种完整的 CAD 流程，用于在 3D FPGA 上实现任意逻辑电路。流程中的分区和放置阶段基于模拟退火算法。此外，路由阶段是 Pathfinder 算法的修改版。模拟结果表明，将 2D FPGA 和 3D FPGA（包括两层）进行比较，电路速度增加了 28.66%，最小通道宽度减小了 29.92%，而总面积增加了 8.86%。最后，将 3D FPGA 中的 2 层和 4 层进行比较，4 层的电路速度和最小通道宽度分别增加了 15.95% 和 15.92%，而总面积仅增加了 1.96%。
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