This paper proposes a novel approach for the generation of memory-efficient table-based function approximation circuits for FPGAs. Given a function f(x) to be approximated in a given interval [x0,x0+a] and a maximum approximation error Ea, the goal is to determine a function table implementation with a minimized memory footprint, i.e., number of entries that need to be stored. Rather than state-of-the-art work performing an even sampling of the given interval by so-called breakpoints and using linear interpolation between two adjacent breakpoints to determine f(x) at the maximum error bound, first, we propose three interval-splitting algorithms to reduce the required memory footprint drastically based on the observation that in sub-intervals of low gradient, a coarser sampling grid may be assumed to satisfy the maximum interpolation error bound. Experiments on elementary mathematical functions show that a large fraction in memory footprint may be saved. Second, a hardware architecture implementing the sub-interval selection, breakpoint lookup and interpolation at a latency of just 9 clock cycles is introduced. Third, within each generated circuit design, BRAMs are automatically instantiated rather than synthesizing the reduced footprint function table using LUT primitives providing an additional degree of resource efficiency.
翻译:本文提出一种创新的方法,用于为 FPGAs 生成记忆高效表基功能近似电路。 鉴于函数 f(x) 将在给定间隔[x0x0+a] 和最大近似误差Ea 中大致排序f(x), 我们的目标是确定函数表执行, 最小的内存足迹, 即需要存储的条目数量。 与以所谓的断点对给定间隔进行偶切的抽样比较的最先进的工作相比, 并使用两个相邻断点之间的线性内插图来确定 F(x) 在最大误差约束时的f(x) 。 首先, 我们建议采用三个间隔算算法, 以在低梯度的次间隔中进行观察, 可以假设一个粗缩的取样网, 以满足最大间错 。 对基本数学函数的实验表明, 可以用所谓的断断点对给定间隔间隔间隔间隔的较大部分进行抽样取样。 其次, 采用硬结构, 仅在9 时钟周期的宽度上进行选择、 断点查看和间插点检查, 。 第三, 利用每个生成的电路段设计中, 将自动地段设计