As programmers turn to software-defined hardware (SDH) to maintain a high level of productivity while programming hardware to run complex algorithms, heavy-lifting must be done by the compiler to automatically partition on-chip arrays. In this paper, we introduce an automatic memory partitioning system that can quickly compute more efficient partitioning schemes than prior systems. Our system employs a variety of resource-saving optimizations and an ML cost model to select the best partitioning scheme from an array of candidates. We compared our system against various state-of-the-art SDH compilers and FPGAs on a variety of benchmarks and found that our system generates solutions that, on average, consume 40.3% fewer logic resources, 78.3% fewer FFs, 54.9% fewer Block RAMs (BRAMs), and 100% fewer DSPs.
翻译:当程序员转向软件定义的硬件(SDH)来保持高生产率,而程序设计硬件来运行复杂的算法时, 编译者必须进行重升, 才能自动分割芯片阵列。 在本文中, 我们引入了自动内存分割系统, 可以快速计算比先前系统更高效的分区方案。 我们的系统使用各种资源节约优化和ML成本模型来从一系列候选人中选择最佳的分区方案。 我们比较了我们的系统, 比较了各种最先进的SDH编译者和FPGAs, 发现我们的系统产生的解决方案平均消耗40.3%的逻辑资源, 减少78.3%的FF, 减少54.9%的区块内存(BRAMs), 减少100%的DSPs。