Symbolic execution is a powerful verification tool for hardware designs, but suffers from the path explosion problem. We introduce a new approach, piecewise composition, which leverages the modular structure of hardware to transfer the work of path exploration to SMT solvers. We present a symbolic execution engine implementing the technique. The engine operates directly over register transfer level (RTL) Verilog designs without requiring translation to a netlist or software simulation. In our evaluation, piecewise composition reduces the number of paths explored by an order of magnitude and reduces the runtime by 97%. Using 84 properties from the literature we find assertion violations in 5 open-source designs including an SoC and CPU.
翻译：符号执行是硬件设计的强大验证工具，但存在路径爆炸问题。我们引入了一种新的方法，即分段组成，通过利用硬件的模块化结构将路径探索的工作转移到 SMT 求解器中。我们介绍了一种实现该技术的符号执行引擎。该引擎可以直接操作寄存器传输级 (RTL) Verilog 设计，而无需将其转换为网络表或进行软件模拟。在我们的评估中，分段组合将所探索的路径数量减少了一个数量级，并将运行时降低了97％。使用来自文献的84个属性，我们在包括 SoC 和CPU 在内的5个开源设计中发现了断言违规情况。
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