三维集成电路绑定前/后测试成本的协同优化方法研究

项目名称： 三维集成电路绑定前/后测试成本的协同优化方法研究

项目编号： No.61306049

项目类型： 青年科学基金项目

立项/批准年度： 2014

项目学科： 无线电电子学、电信技术

项目作者： 刘军

作者单位： 合肥工业大学

项目金额： 25万元

中文摘要： 三维电路能够有效地克服二维电路互连线延迟和功耗的瓶颈，是延续摩尔定律的有效方法。然而，三维电路的测试却面临很大的挑战，测试成本过高就是其中亟需解决的一个主要问题。本项目通过绑定前复用绑定后的测试架构和TSV数量的约束来减少硬件开销，研究减少三维电路绑定前/后测试总时间的有效方法，达到降低绑定前/后测试总成本的目的。具体研究内容如下：(1)研究基于广播结构的三维电路扫描链设计方法，利用多个扫描单元共享测试数据的方式来减少测试时间，并通过两级测试响应压缩来提高TSV和输出引脚的利用效率；（2）研究三维嵌入式芯核测试外壳扫描链的设计方法，通过平衡绑定前/后各条测试外壳扫描链的长度，以减少测试时间；（3）探索基于分布式压缩的三维系统芯片测试访问机制设计和测试调度方法，利用"空闲"的测试通道对多核进行并行测试，减少三维系统芯片的测试时间。通过本项目的研究，将为三维电路的测试提供有效的低成本解决方案。

中文关键词： 三维集成电路；测试外壳扫描链；扫描树；测试时间；测试成本

英文摘要： Three dimensional integrated circuits(3D ICs) can effectively overcome the bottlneck of interconnects delay and power consumption in 2D ICs.However, there are many grand challenges for 3D ICs test, one of which is the high test cost. The project intend to reduce 3D ICs total test cost for pre-bond and post-pond testing. The hardware overhead is reduced by reusing the post-bond test architecture in pre-bond test and constraining TSVs number. New optimization techniques are explored to reduce pre-bond and post-bond test time. The three themes in the proposed research are as following: (1)Investigating the design of broadcast-based scan chain in 3D ICs. The scan chain architecture can effectively reduce test time by sharing test data among scan cells. Besides, two-level test response compactor is configured to improve the efficiency of TSVs and test output pads. (2) Exploring the design of wrapper scan chains in 3D embedded cores. The theme aims at reducing test time by balancing the length of wrapper scan chains in pre-bond and post-bond test. (3)Exploring the test access mechanism(TAM) design and test schedule method based on distributed compression technique for 3D SoC. The "idle channels" are utilized to test cores in parallel to reduce test time. The project will present low test cost techniques for 3D ICs t

英文关键词： 3D ICs；test wrapper scan chains；scan tree；test time；test cost