Bayesian Network Structure Learning using Digital Annealer

Annealing processors, which solve a quadratic unconstrained binary optimization (QUBO), are a potential breakthrough in improving the accuracy of score-based Bayesian network structure learning. However, currently, the bit capacity of an annealing processor is very limited. To utilize the power of annealing processors, it is necessary to encode score-based learning problems into QUBO within the upper bound of bits. In this paper, we propose a novel approach with the decomposition of candidate parent sets. Experimental results on benchmark networks with $37$ to $223$ variables show that our approach requires lesser bits than the bit capacity of the fourth-generation Fujitsu Digital Annealer, a fully coupled annealing processor developed with semiconductor technology. Moreover, we demonstrate that the Digital Annealer with our conversion method outperforms existing algorithms on some benchmark networks. It is expected that our approach promotes the utility of annealing processors in learning the Bayesian network.