To provide data and code confidentiality and reduce the risk of information leak from memory or memory bus, computing systems are enhanced with encryption and decryption engine. Despite massive efforts in designing hardware enhancements for data and code protection, existing solutions incur significant performance overhead as the encryption/decryption is on the critical path. In this paper, we present Sealer, a high-performance and low-overhead in-SRAM memory encryption engine by exploiting the massive parallelism and bitline computational capability of SRAM subarrays. Sealer encrypts data before sending it off-chip and decrypts it upon receiving the memory blocks, thus, providing data confidentiality. Our proposed solution requires only minimal modifications to the existing SRAM peripheral circuitry. Sealer can achieve up to two orders of magnitude throughput-per-area improvement while consuming 3x less energy compared to the prior solutions.
翻译:为了提供数据和代码保密性,并减少内存或内存总线信息泄漏的风险,计算机系统用加密和解密引擎得到加强。尽管在设计数据和代码保护硬件增强装置方面做了大量努力,但现有解决方案在关键路径上的加密/解密过程中需要大量性能管理。在本文中,我们介绍Seler,一个高性能和低管理水平的SRAM内存加密引擎,利用SRAM子阵列的大规模平行和比特线计算能力。Serler加密数据,然后将数据发送出芯片,并在接收内存区块时解密,从而提供数据保密性。我们提议的解决方案只需要对现有SRAM外围电路进行最低限度的修改。Sealer可以达到两个数量级的吞吐量-每个区域改进,同时比先前的解决方案少消耗3x能量。