Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (IC) and fabricate them in a third-party foundry. Unauthorized IC copies cost these companies billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after the synthesis tools embed the semantic information into the netlist. We propose ASSURE to protect hardware IP modules operating on the register-transfer level (RTL) description. The RTL approach has three advantages: (i) it allows designers to obfuscate IP cores generated with many different methods (e.g., hardware generators, high-level synthesis tools, and pre-existing IPs). (ii) it obfuscates the semantics of an IC before logic synthesis; (iii) it does not require modifications to EDA flows. We perform a cost and security assessment of ASSURE.
翻译:半导体设计公司正在整合专有知识产权(IP)块,以建立自定义集成电路(IC),并将其制成第三方铸造。未经授权的IC副本每年耗资这些公司数十亿美元。虽然为硬件IP混淆提出了几种方法,但它们在门级网络列表上运作,即在合成工具将语义信息嵌入网络列表之后。我们建议SURE保护在登记-转让水平描述下运作的硬件IP模块。RTL方法有三个优点:(一)允许设计者混淆以多种不同方法(例如硬件生成器、高级合成工具和原有IP)生成的IP核心。 (二)在逻辑合成之前,它模糊了IC的语义;(三)它不需要修改EDA流。我们对ASURE进行成本和安全评估。