Privacy and security have rapidly emerged as priorities in system design. One powerful solution for providing both is privacy-preserving computation, where functions are computed directly on encrypted data and control can be provided over how data is used. Garbled circuits (GCs) are a PPC technology that provide both confidential computing and control over how data is used. The challenge is that they incur significant performance overheads compared to plaintext. This paper proposes a novel garbled circuit accelerator and compiler, named HAAC, to mitigate performance overheads and make privacy-preserving computation more practical. HAAC is a hardware-software co-design. GCs are exemplars of co-design as programs are completely known at compile time, i.e., all dependence, memory accesses, and control flow are fixed. The design philosophy of HAAC is to keep hardware simple and efficient, maximizing area devoted to our proposed custom execution units and other circuits essential for high performance (e.g., on-chip storage). The compiler can leverage its program understanding to realize hardware's performance potential by generating effective instruction schedules, data layouts, and orchestrating off-chip events. In taking this approach we can achieve ASIC performance/efficiency without sacrificing generality. Insights of our approach include how co-design enables expressing arbitrary GC programs as streams, which simplifies hardware and enables complete memory-compute decoupling, and the development of a scratchpad that captures data reuse by tracking program execution, eliminating the need for costly hardware managed caches and tagging logic. We evaluate HAAC with VIP-Bench and achieve a speedup of 608$\times$ in 4.3mm$^2$ of area.
翻译:作为系统设计的优先事项,隐私和安全迅速出现。提供两者的强大解决方案之一是隐私保护计算,其功能直接根据加密数据计算,对数据使用方式的控制可以提供。加固电路(GC)是一种PPC技术,既提供机密计算,又对数据使用方式的控制。挑战在于,与平文本相比,它们产生大量的性能管理管理。本文建议建立一个名为HAAC的新颖的加压电路加速器和编译器,以减少性能管理管理,使隐私保护计算更加实用。HAAC是一个硬件软件共同设计。由于程序在编译时间完全为人所知,因此,GARC是共同设计(GC)的增值设计师,即所有依赖性、存储程序访问和控制流程都是固定的。HAAC的设计理念是保持硬件简单和高效,最大限度地增加用于我们拟议定制执行单位和其他对高性能必不可少的电路路段(例如,在芯存储中),编译者可以利用其程序来实现硬件的性能潜力,通过生成有效的电算表表、数据管理性能跟踪和操控数据流,从而实现内部智能操作,从而实现硬化的节流的节能,从而实现内部节能。