逻辑错误屏蔽的近似电路逻辑综合多目标优化方法研究

项目名称： 逻辑错误屏蔽的近似电路逻辑综合多目标优化方法研究

项目编号： No.61502327

项目类型： 青年科学基金项目

立项/批准年度： 2016

项目学科： 自动化技术、计算机技术

项目作者： 陶砚蕴

作者单位： 苏州大学

项目金额： 21万元

中文摘要： 集成电路工艺向纳米级发展，芯片尺寸压缩、工作电压下降，逻辑错误率不断提高，逻辑错误屏蔽已成为电路设计的挑战性问题。近似电路以小面积、低功耗代价获得较高错误屏蔽性能，在芯片有限内部资源和低能耗需求下，对近似电路逻辑综合优化研究具有重要实际意义。近似电路逻辑综合优化是对错误覆盖率、面积和功耗三个互冲突目标的同时优化。本课题研究一种近似电路综合多目标优化方法。首先确立多级逻辑函数节点的0/1相位选择机制和多路径节点处理机制，保证全局函数单相近似，满足错误屏蔽充要条件；建立面积、功耗与错误覆盖率的近似电路综合多目标优化模型，引入遗传算法和小生境机制，设计均匀进化算子，保持群体多样性，提高非劣解沿Pareto占优面的均匀分布度；确立优先级偏好的近似电路非支配排序策略，提高全局收敛性和计算效率，获得容错性价比高的近似电路解集。通过对基准电路测试，验证近似电路逻辑错误屏蔽有效性和多目标遗传算法优越性。

中文关键词： 容错设计；近似电路；逻辑综合；多目标优化；Pareto解集

英文摘要： As the development of the integrated circuits to nano-level, with chip size reduction, high frequency, and low voltage, logical error rate increases largely in the combinational circuits. Logical error tolerance has become a challenge for human in integrated circuit design. The approximation circuit has a feature with low area and power. With limited resources inside the chip, it is meaningful to make efforts on the optimization on the synthesis of approximation circuit for logical error tolerance. The optimization on the synthesis of approximation circuit is to optimize the area, power, and error coverage rate simultaneously. This issue intends to explore a multi-objective optimization approach for approximate logic synthesis. First, we propose a node-0/1 phase selection strategy based on multi-level logic, together with a node process under multi-path. The strategy guarantees the circuit approximation on single on set or off-set so that the necessary and sufficient condition for logical error masking is meet. Then, the multi-objective model for approximate circuit based on area, power and error coverage rate is established. We employ the genetic algorithm with niches mechanism, design the even genetic operators, and keep the diversity of population. These improve the uniform distribution of non-dominated solutions on Pareto dominant surface. Finally, a non-dominated strategy with priority preference for sorting approximate circuits is proposed to accelerate the global convergence and efficiency of computation. The Pareto solutions for approximate circuits with high performance are achieved. By the tests comprehensively on benchmarks, the efficiency of the multi-objective optimization approach in the synthesis of approximate circuit for logical error masking will be proven.

英文关键词： error tolerance;approximate circuit;logic synthesis;multi-objective optimization;Pareto solutions