数字电路双逻辑综合关键技术研究

项目名称： 数字电路双逻辑综合关键技术研究

项目编号： No.61471211

项目类型： 面上项目

立项/批准年度： 2015

项目学科： 无线电电子学、电信技术

项目作者： 王伦耀

作者单位： 宁波大学

项目金额： 72万元

中文摘要： 数字逻辑电路既可以采用基于与/或/非运算的传统布尔(Traditional Boolean, TB)逻辑，也可以采用基于与/异或运算的Reed-Muller(RM)逻辑来实现。相比于单一的TB逻辑或RM逻辑，事实上，大多数电路本身就是二种逻辑的混合体，因此，理想的电路综合策略应该是同时采用TB逻辑和RM逻辑相结合的双逻辑综合。 本项目的双逻辑综合策略是通过将待优化逻辑覆盖中搜索、拆分成适合TB逻辑和RM逻辑的子覆盖，并分别用TB和RM逻辑实现，进而达到逻辑优化目的。相应的关键技术包括：适合不同逻辑实现的逻辑覆盖探测技术、逻辑覆盖拆分、大RM函数混合极性逻辑综合，逻辑等效验证，复合逻辑门在逻辑映射运用等方面。项目的研究成果将丰富逻辑综合理论和方法，同时建立一个双逻辑综合平台。

中文关键词： 双逻辑；逻辑综合；逻辑拆分；工艺映射；EDA

英文摘要： The function of digital circuits can be represented as either AND/OR/NOT based traditional Boolean （briefly, TB） forms or AND/XOR based Reed-Muller forms (briefly, RM). Compare to the circuits which are realized with only TB logic or RM logic, in the fact, most of the circuits are the mixture of the TB logic and RM logic. Therefore the good way for the logic synthesis and optimization of a circuit is implementation both the TB logic and RM logic at the same time, namely dual logic. The methodology of the dual logic synthesis in this project is by searching and splitting a logic cover into sub-covers and implementing them with TB logic and RM logic respectively which are suitable for TB and RM logic implementation. And the corresponding key techniques for the dual logic synthesis include: logic detection techniques for the different logic implementation, logic decomposition techniques, functional verification under dual logic, technology mapping using complex gates, and so on. The research results of this project will enrich the theory and method in logic synthesis. And a platform for dual logic synthesis will also be offered in this project.

英文关键词： dual logic;logic synthesis;logic decomposition;technology mapping;EDA