SpinNNNAK 2 混合数字神经元计算处理元素架构 (The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing)

Sebastian Höppner,Yexin Yan,Andreas Dixius,Stefan Scholze,Johannes Partzsch,Marco Stolba,Florian Kelber,Bernhard Vogginger,Felix Neumärker,Georg Ellguth,Stephan Hartmann,Stefan Schiefer,Thomas Hocker,Dennis Walter,Genting Liu,Jim Garside,Steve Furber,Christian Mayr

This paper introduces the processing element architecture of the second generation SpiNNaker chip, implemented in 22nm FDSOI. On circuit level, the chip features adaptive body biasing for near-threshold operation, and dynamic voltage-and-frequency scaling driven by spiking activity. On system level, processing is centered around an ARM M4 core, similar to the processor-centric architecture of the first generation SpiNNaker. To speed operation of subtasks, we have added accelerators for numerical operations of both spiking (SNN) and rate based (deep) neural networks (DNN). PEs communicate via a dedicated, custom-designed network-on-chip. We present three benchmarks showing operation of the whole processor element on SNN, DNN and hybrid SNN/DNN networks.

翻译：本文介绍第二代SpinNNAker芯片的处理要素结构,该芯片在22nm FDSOI中实施。在电路一级,芯片的特点是偏向近临界线操作的适应性体,以及由跳动活动驱动的动态电压和频率缩放。在系统一级,加工以ARM M4核心为中心,类似于第一代SpinNAker的处理者中心结构。为了加速子任务的运作,我们为跳动(SNN)和基于(深)神经网络的数字操作添加了加速器。PE通过专用的定制网络在芯片上进行通信。我们提出了三个基准,显示SNN、DNN和混合的SNNN/DNN网络上整个处理器元的运行情况。