Viterbi decoders are widely used in communication systems, natural language processing (NLP), and other domains. While Viterbi decoders are compute-intensive and power-hungry, we can exploit approximations for early design space exploration (DSE) of trade-offs between accuracy, power, and area. We present Locate, a DSE framework that uses approximate adders in the critically compute and power-intensive Add-Compare-Select Unit (ACSU) of the Viterbi decoder. We demonstrate the utility of Locate for early DSE of accuracy-power-area trade-offs for two applications: communication systems and NLP, showing a range of pareto-optimal design configurations. For instance, in the communication system, using an approximate adder, we observe savings of 21.5% area and 31.02% power with only 0.142% loss in accuracy averaged across three modulation schemes. Similarly, for a Parts-of-Speech Tagger in an NLP setting, out of 15 approximate adders, 7 report 100% accuracy while saving 22.75% area and 28.79% power on average when compared to using a Carry-Lookahead Adder in the ACSU. These results show that Locate can be used synergistically with other optimization techniques to improve the end-to-end efficiency of Viterbi decoders for various application domains.
翻译:Viterbi译码器广泛用于通信系统、自然语言处理(NLP)和其他领域。虽然Viterbi译码器具有计算强度和动力需求高的特点,但我们可以利用近似方法早期进行设计空间探索(DSE),以权衡准确性、功率和面积。我们提出了一种DSE框架Locate,该框架使用近似加法器来处理Viterbi译码器中关键的计算和功耗强度的加入-比较-选择单元(ACSU)。我们展示了Locate的实用性,用于通信系统和NLP的准确度-功率-面积的早期DSE的配置。例如,在通信系统中,使用近似加法器,我们观察到在三种调制方案的平均情况下,每个方案损失了0.142%的准确度,但节省了21.5%的面积和31.02%的功率。同样,在NLP设置中的词性标注器中,使用15个近似加法器中的7个报告100%的准确性,同时与在ACSU中使用Carry-Lookahead加法器相比,平均节省22.75%的面积和28.79% 的动力需求。这些结果表明,Locate可以与其他优化技术协同使用,以提高Viterbi解码器的端到端效率,适用于各种应用领域。