We designed and implemented a direct memory access (DMA) architecture of PCI-Express(PCIe) between Xilinx Field Program Gate Array(FPGA) and Freescale PowerPC. The DMA architecture based on FPGA is compatible with the Xilinx PCIe core while the DMA architecture based on POWERPC is compatible with VxBus of VxWorks. The solutions provide a high-performance and low-occupancy alternative to commercial. In order to maximize the PCIe throughput while minimizing the FPGA resources utilization, the DMA engine adopts a novel strategy where the DMA register list is stored both inside the FPGA during initialization phase and inside the central memory of the host CPU. The FPGA design package is complemented with simple register access to control the DMA engine by a VxWorks driver. The design is compatible with Xilinx FPGA Kintex Ultrascale Family, and operates with the Xilinx PCIe endpoint Generation 1 with lane configurations x8. A data throughput of more than 666 MBytes/s(memory write with data from FPGA to PowerPC) has been achieved with the single PCIe Gen1 x8 lanes endpoint of this design, PowerPC and FPGA can send memory write request to each other.
翻译:我们设计并实施了Xilinx现场方案门阵列和自由电源PC之间的PCI-Express(PDA)直接内存(DMA)架构。基于 FPGA的DMA架构与Xilinx PCIe核心兼容,而基于POWERPC的DMA架构与VxWorksVxBus兼容。解决方案提供了商业上高性能和低使用率的替代产品。为了最大限度地实现PCIE的吞吐量,同时尽量减少FPGA资源的利用,DMA引擎采用了一种新颖的战略,在FPGA的初始阶段和主机中央记忆中,DMA登记名单同时储存在FPGA内。 FPGA的设计包与基于VxWorks驱动器控制DMA引擎的简单注册访问相配合。该设计与Xlinx FPGA Kintex Ultra规模家庭兼容,并与Xlinx PCIE Plation 1级配置X8. 数据通过超过66MBytes/s的数据在FA/GPA 1 PrinPA 的每个电压-PA1 笔记号的SIMPA/CFPASLA/CFPA/PA 的SendPADADR) 的每个用户端端要求的SDA/PAFPA-SDS-S-S-S-S-S-PA-PA-S-PA-S-S-PDFA-S-PA-S-PA-P-P-P-P-PLTFP-S-P-P-S-S-P-S-S-S-S-S-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-P-PA-P-P-P-P-P-P-P-P-P-P-P-P-P-P-PA-P-P-P-P-P-P-P-P-PA-P-P-PA-P-P-P-P-P-