This paper presents a novel, non-standard set of vector instruction types for exploring custom SIMD instructions in a softcore. The new types allow simultaneous access to a relatively high number of operands, reducing the instruction count where applicable. Additionally, a high-performance open-source RISC-V (RV32 IM) softcore is introduced, optimised for exploring custom SIMD instructions and streaming performance. By providing instruction templates for instruction development in HDL/Verilog, efficient FPGA-based instructions can be developed with few low-level lines of code. In order to improve custom SIMD instruction performance, the softcore's cache hierarchy is optimised for bandwidth, such as with very wide blocks for the last-level cache. The approach is demonstrated on example memory-intensive applications on an FPGA. Although the exploration is based on the softcore, the goal is to provide a means to experiment with advanced SIMD instructions which could be loaded in future CPUs that feature reconfigurable regions as custom instructions. Finally, we provide some insights on the challenges and effectiveness of such future micro-architectures.
翻译：本文介绍了一套用于在软核中探索定制的 SIMD 指令的新型、非标准矢量指示类型。 新型允许同时访问数量相对较多的操作器, 并酌情减少指示计数。 此外, 引入了高性能开放源的 RISC- V( RV32 IM) 软核, 优化探索定制的 SIMD 指令和流体性能。 通过提供用于HDL/ Verilog 中教学开发的指导模板, 有效的 FPGA 指令可以用很少的低级代码线来开发。 为了改进定制的 SIMD 指令性能, 软核缓存的级别等级对带宽度进行了优化, 例如对最后一级缓存的非常宽的区块进行优化。 这种方法在 FPGA 的记忆密集应用中得到了示范。 尽管探索以软核为基础, 目的是提供一种实验手段, 将高级的 SIMD 指令装入未来的 CUPS, 其特征可作为定制指令。 最后, 我们对未来微型结构的挑战和有效性提供了一些见解。
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