门电路复合应力模式下NBTI的退化机制及建模

项目名称： 门电路复合应力模式下NBTI的退化机制及建模

项目编号： No.61204038

项目类型： 青年科学基金项目

立项/批准年度： 2013

项目学科： 信息四处

项目作者： 李小进

作者单位： 华东师范大学

项目金额： 28万元

中文摘要： 负偏压温度不稳定性（NBTI）是制约纳米器件/电路性能及寿命的关键因素。其形成机理复杂，较难准确完整地表征。特别在应力多变的低功耗模式下，准确退化模型的缺失已成为制约纳米集成电路可靠性设计的主要瓶颈。本项目以门电路复合应力模式下的NBTI退化特性为研究对象，对其退化规律、机制和数学建模进行研究。具体内容包括：数值求解三种不同SiO2/多晶硅栅界面边界条件下的反应扩散（R-D）方程，分析复合应力驱动模式下Si/SiO2界面、栅氧化层和多晶硅栅中H2/H连续扩散浓度分布变化规律；建立复合应力模式下长时动态△Vth退化数学模型；设计基于延迟单元的退化测试电路，并进行测试；编写UDRM函数并仿真延迟数据通道，对比仿真与测试，修正并完善本项目拟提出的△Vth退化数学模型。本项目旨在揭示多变应力模式下的NBTI退化规律及其形成机制，为纳米集成电路可靠性设计提供准确的NBTI退化模型。

中文关键词： 负偏压温度不稳定性；器件退化；建模；复合应力；门电路

英文摘要： Negative Bias Temperature Instability (NBTI) is one of the most significant transistor reliability impediment in nanometer device and circuit. It's difficult to describe the accurate physical mechanism of NBTI due to its sophisticated behaviors and various explanation of hypothesis. The lack of accurate NBTI aging model becomes the bottleneck of integrated circuit design in reliability. In this project, the research focuses will be casted on the NBTI aging characteristic of logic gate under compound stress, including its generation discipline, mechanism and degradation model. Considering the finite oxide thickness which may lead to three different boundary hypothesis including the reflective and the absorbent, the third one assumes that the H2/H would diffuse across the interface of SiO2/Poly-Si and deep into polysilicon. The reaction-diffusion (R-D) equation for the generation/passivation of the interface traps would be described, analyzed and numerical solved precisely. The distribution change of H2/H under various compound stress on the surface of Si/SiO2, inside SiO2 and polysilicion will be calculated and investigated. Therefore, the mathematic model for long term dynamic degradation of △Vth will be built up based on the solved results of R-D model. Consequently, the test circuits of aging will be designed

英文关键词： NBTI；Device Degradation；Modeling；Compound Stress；Logic gate