The current workloads and applications are highly diversified, facing critical challenges such as the Power Wall and the Memory Wall Problem. Different strategies over the multiple levels of Caches have evolved to mitigate these problems. Also, to work with such diversified applications, the Asymmetric Multi-Core Processor (AMP) presents itself as a viable solution. In this paper, we study the performance of L2 and Last Level Cache for different cache partitions against various AMP configurations. In addition, this study investigates the optimal cache partitioning for a collection of Multi-threaded benchmarks from PARSEC and SPLASH2 benchmark suites under medium-sized inputs. We have studied the effect of block replacement strategies and their impact on the key metrics such as total on-chip power consumption and L2 \& LLC Miss rates. Our study presents an intermediate cache design for AMPs between the two extremities of fully shared and fully private L2 \& LLC level Cache, which helps achieve the desired power values and optimal cache miss penalties.
翻译:非对称多核处理器中分区缓存的性能研究
翻译后的摘要:
当前的工作负载和应用程序高度多样化,面临诸如功耗墙和存储器墙问题等关键挑战。在不同的缓存层次上已经出现了多种策略以缓解这些问题。此外,为了应对这种多样化的应用程序,非对称多核处理器 (AMP) 成为一种可行的解决方案。本文研究了不同缓存分区的 L2 和最后一级缓存的性能,针对不同的 AMP 配置进行了研究。在中等大小的输入下,本研究调查了一系列多线程基准测试 (来自 PARSEC 和 SPLASH2 基准测试套件) 的最佳缓存分区。我们研究了块替换策略的影响,以及它们对总片上功耗和 L2 和 LLC 缺失率等关键指标的影响。本研究提出了一种 AMP 中间缓存设计,介于完全共享和完全私有的 L2 和 LLC 级缓存两个极端之间,有助于实现所需的功耗值和缓存缺失 Penalty 的最优化。