Understanding Tool Synthesis Behavior and Safe Finite State Machine Design

High-reliability design requires understanding synthesis tool behavior and best practices. Detection and protection against illegal states and transitions is important for critical Finite State Machines (FSMs) within high reliability applications. Single Event Upsets (SEUs) probability is increasing with decreasing circuit dimensions and voltage [1]. SEU handling must be analyzed post optimization to ensure designed protections are still functional. In this work the default behavior of three synthesis tools interacting with high reliability FSMs is discussed. Post-synthesis netlists of test FSMs are analyzed for optimization induced changes that affect reliability during a SEU. Best practices are proposed to curtail aggressive optimizers.