VWSIM is a circuit simulator for rapid, single-flux, quantum (RSFQ) circuits. The simulator is designed to model and simulate primitive-circuit devices such as capacitors, inductors, Josephson Junctions, and can be extended to simulate other circuit families, such as CMOS. Circuit models can be provided in the native VWSIM netlist format or as SPICE-compatible netlists, which are flattened and transformed into symbolic equations that can be manipulated and simulated. Written in the ACL2 logic, VWSIM provides logical guarantees about each of the circuit models it simulates. Note, our matrix solving and evaluation routines use Common Lisp floating-point numbers, and work is ongoing to admit these models into ACL2. We currently use VWSIM to help us design self-timed, RSFQ-based circuits. Our eventual goal is to prove properties of RSFQ circuit models. The ACL2-based definition of the VWSIM simulator offers a path for specifying and verifying RSFQ circuit models.
翻译:VWSIM是快速、单流、量子(RSFQ)电路的电路模拟器。模拟器的设计是为了模拟和模拟电容器、导管、Josephson交叉点等原始电路装置,可以推广到模拟其他电路家庭,如CMOS。 电路模型可以以本地VWSIM网络列表格式或SPICE兼容式网络列表提供,这些模型被扁平并转化成可以操纵和模拟的象征性方程式。VCL2逻辑,VWSIM为每个模拟电路模型提供逻辑保证。注意,我们的矩阵解析和评估程序使用通用升浮点编号,目前正在将这些模型纳入ACL2。我们目前使用VWSIM来帮助我们设计自定时的、基于RSFQ的电路路。我们的最终目标是证明RSFQ电路模型的特性。基于ACL2-基于VSIM模拟器的ACL2定义提供了具体和核实RSFQ电路模型的路径。