We introduce techniques for proving superlinear conditional lower bounds for polynomial time problems. In particular, we show that CircuitSAT for circuits with m gates and log(m) inputs (denoted by log-CircuitSAT) is not decidable in essentially-linear time unless the exponential time hypothesis (ETH) is false and k-Clique is decidable in essentially-linear time in terms of the graph's size for all fixed k. Such conditional lower bounds have previously only been demonstrated relative to the strong exponential time hypothesis (SETH). Our results therefore offer significant progress towards proving unconditional superlinear time complexity lower bounds for natural problems in polynomial time.
翻译:我们引入了多种时间问题的超线性有条件下限验证技术。 特别是, 我们显示, 带M门和日志输入( 由日志- CircuitSAT 表示) 的电路的环形卫星( CircuitSAT ) 无法在基本线性时间内进行分层, 除非指数时间假设( ETH) 是假的, k- Clique 在所有固定 k 的图形大小上基本上线性分层。 这种条件性下限以前只比强的指数时间假设( SETH ) 得到证明。 因此, 我们的结果为证明多线性超线性时间复杂性对于多线性时间的自然问题来说是无条件超线性时间复杂性较低的。