Comprehensive Survey of Ternary Full Adders: Statistics, Corrections, and Assessments

The history of ternary adders goes back to more than six decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This paper aims to conduct a survey to be familiar with the utilized design methodologies and logic families and their prevalence. Although the number of papers about this topic is high, almost none of the previously presented TFAs are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. Moreover, they could have been simplified even further by assuming a partial TFA where the voltage of the output carry is either 0V or VDD. This way, less static power would be dissipated. Therefore, a strong motivation is to correct and enhance the previous designs. Furthermore, different simulation setups, which are not realistic enough, have been taken into account. Therefore, the simulation results reported in the previous papers are neither comparable nor entirely valid. Among the 75 papers in which a new design of TFA has been given, 11 papers are selected, simplified, and simulated in this paper. Simulations are carried out by HSPICE and 32nm CNFET technology while considering a standard test-bed and a complete input pattern to reveal the maximum cell delay. The simplified partial TFAs outperform their original versions in delay, power, and transistor count.