2.5D chiplet systems have been proposed to improve the low manufacturing yield of large-scale chips. However, connecting the chiplets through an electronic interposer imposes a high traffic load on the interposer network. Silicon photonics technology has shown great promise towards handling a high volume of traffic with low latency in intra-chip network-on-chip (NoC) fabrics. Although recent advances in silicon photonic devices have extended photonic NoCs to enable high bandwidth communication in 2.5D chiplet systems, such interposer-based photonic networks still suffer from high power consumption. In this work, we design and analyze a novel Reconfigurable power-efficient and congestion-aware Silicon Photonic 2.5D Interposer network, called ReSiPI. Considering run-time traffic, ReSiPI is able to dynamically deploy inter-chiplet photonic gateways to improve the overall network congestion. ReSiPI also employs switching elements based on phase change materials (PCMs) to dynamically reconfigure and power-gate the photonic interposer network, thereby improving the network power efficiency. Compared to the best prior state-of-the-art 2.5D photonic network, ReSiPI demonstrates, on average, 37% lower latency, 25% power reduction, and 53% energy minimization in the network.
翻译:2.5D 芯片系统已经提出来提高大型芯片的低生产产值。 但是,通过电子插座将芯片连接起来给干涉器网络带来了很高的交通负荷。硅光子技术已经展示了巨大的希望,可以处理芯片内部网络在芯片上(NOC)织物中低悬浮的大量交通。虽然硅光子装置最近的进展扩大了光子点点点,使2.5D芯片系统中的高带宽通信,但这种基于互接器的光子网络仍然受到高电耗的影响。在这项工作中,我们设计并分析一个新型的可配置电节能和拥堵性硅光子2.5D 光子网络,称为ReSiPI。考虑到运行时间的流量,ReSIPI能够动态地部署硅光子网间网门,以改善整个网络的拥挤状况。ReSIPI还利用基于阶段变化材料(PCMs)的转换元素进行动态重组和开启电源源源网,从而提高网络的电源节能效率,从而改进网络的节能效率。