基于3-D EFD方法发展适用于传统及TSV技术的互连系统寄生电容模型研究

项目名称： 基于3-D EFD方法发展适用于传统及TSV技术的互连系统寄生电容模型研究

项目编号： No.61306042

项目类型： 青年科学基金项目

立项/批准年度： 2014

项目学科： 无线电电子学、电信技术

项目作者： 赵巍

作者单位： 北京大学

项目金额： 29万元

中文摘要： 随着超大规模集成电路制造进入亚45纳米时代，寄生电容对电路性能的影响问题越来越突出。互连系统的尺寸变化及先进工艺和TSV技术的采用，导致传统建模方法很难准确提取先进互连系统的寄生电容，从而无法完成对应纳米CMOS电路有效设计与性能优化。基于以上背景，本研究提出"基于3-D EFD方法发展适用于传统及TSV技术的互连系统寄生电容模型研究"课题，在典型互连结构3-D电场分布分析和有效划分基础上，从电场基本原理层面建立覆盖TSV技术的纳米CMOS互连系统的寄生电容模型。 发展的模型应能针对纳米CMOS先进互连技术和3-D堆叠集成电路中的TSV互连技术计算对应的寄生电容，预言几何结构和工艺尺度变化对寄生电容和电路性能的影响规律，从而为对应的纳米电路设计和性能优化奠定仿真基础。

中文关键词： CMOS互连系统；TSV互连技术；电容模型；耦合电容；电路设计优化

英文摘要： With rapid development of ultra large scale integrated circuits (ULSI) technology, the extraction of parasitic capacitances, which is essential in the analysis of CMOS circuits, becomes more and more difficult. First of all, it is increasingly challenging to extract the capacitances from back-end-of-line (BEOL) interconnect structures with ever shrinking sizes and modern technologies. Second, the 3-D through silicon via (TSV) technology, which is used extensively in 3-D integrated circuits, typically has complex structures, which is difficult to analyze its parasitic capacitance. The most importantly, the traditional modeling method of empirical fitting poses a formidable hurdle to develop a universal model for common CMOS interconnect and TSV interconnect. To solve the above issues in CMOS technology, we propose the project of "parasitic capacitance modeling of CMOS interconnect including traditional and TSV based on 3-D EFD method". The proposal target is to build compact capacitance models for both traditional BEOL interconnect and 3-D TSV interconnect, based on the analyzing of the electric field decomposition (EFD) between metal structures. The proposed model should be able to calculate parasitic capacitances for advanced interconnect structures, such as the copper diffusion resist layer and air gap tech

英文关键词： CMOS interconnect system；TSV interconnect；Capacitance model；Coupling capacitance；Circuit design and optimization