SOI高压器件荷致高场理论与新结构

项目名称： SOI高压器件荷致高场理论与新结构

项目编号： No.60806025

项目类型： 青年科学基金项目

立项/批准年度： 2009

项目学科： 金属学与金属工艺

项目作者： 罗小蓉

作者单位： 电子科技大学

项目金额： 21万元

中文摘要： SOI技术因其具有高速、低功耗和抗辐照等优点而备受关注。SOI LDMOS具有低耐压和自加热效应的缺点，限制其在高压功率领域的应用;且无统一理论指导SOI横向高压器件纵向耐压的设计。 项目围绕SOI器件的耐压问题，从耐压理论、器件结构和模型方面研究。提出SOI高压器件荷致高场理论，通过引入电荷增强埋层电场而提高耐压。据此，提出系列SOI横向高压器件结构，包括具有双面电荷槽部分SOI ((DT PSOI)，复合埋层SOI (CBL SOI) 以及基于自隔离技术的具有埋N岛的集成SOI(BNIL SOI) LDMOSFETs。利用埋介质上方束缚的电荷使埋层电场从常规SOI LDMOS的120V/um以下增至300V/um以上，同时，硅窗口使衬底参与耐压并提供传热通道，以提高耐压并缓解自热效应。开发图形埋层SOI材料的制备工艺，研制720V的DT PSOI，730V CBL SOI及660V BNIL SOI LDMOSFETs。 本项目是与国际同步的应用基础研究。发表论文30篇，SCI收录17篇，含IEEE EDL和TED 9篇。申请美国发明专利2项，PCT 1项，授权3项中国发明专利。

中文关键词： SOI;电场;电荷;调制;击穿电压

英文摘要： Silicon-on-insulator(SOI)technology have attracted much attention for its high speed, low power loss and perfect irradiation hardness. However, SOI lateral double-diffused metal-oxide-semiconductor (LDMOS) field effect transistors(LDMOSFETs) suffer a low breakdown voltage and self-heating effect because the buried oxide (BOX) layer prevents the depletion region extending into substrate and cuts off the conduction heat path to heat sinker. They limit the application of SOI technology in high-voltage and high-power fields. Furthermore, there is no a unified principle which can be used to design SOI lateral high voltage devices so as to enhance the vertical breakdown voltage. In this project, the breakdown theory, the novel device structures and breakdown analytical models are presented and researched. Especially, the theory of which charges enhance the electric field (E-field) strength in the buried dielectric is proposed for SOI devices, wherein the breakdown voltages are improved owing to the enhanced the E-field strength of the BOX. Based on these theories, a serials of novel high voltage SOI device structures are proposed and investigated theoretically and experimentally, such as partial SOI (PSOI) LDMOS with Double-sided charge Trenches (DT) (DT PSOI), SOI LDMOS with a compound buried layer (CBL SOI), and an integratable SOI LDMOS with buried n-island on p-SOI layer (BNIL SOI) in a self-isolation SOI ICs. The E-field strength of the BOX is increased from 120V/um in the conventional SOI LDMOS to above 300V/um by charges located in the trenches. For PSOI devices, the Si window not only makes the substrate share the BV, but also offers a heat conduction path, resulting in an improved BV and a reduced self-heating effect. A fabrication process for SOI wafer with a patterned buried layer is developed, and the 720V DT PSOI LDMOS with double-sided charge trenches, 730V CBL SOI LDMOS, and 660V integratable BNIL SOI LDMOS based on the self-isolation technology are manufactured. The experimental results verify the theoretical and simulated results. The research is synchronized with the international foundamental application. 30 papers supported by this project are published, in which 17 papers are incited by SCI, including 9 papers on IEEE EDL and IEEE T-ED. 2 USA Patents and 1 PCT patent are applied. 7 invention patents of China are applied, with 3 authorized.

英文关键词： SOI;electric field; charge; modulation; breakdown voltage