亚10纳米集成电路光刻技术与耦合工艺变动性的多栅极晶体管模型研究

项目名称： 亚10纳米集成电路光刻技术与耦合工艺变动性的多栅极晶体管模型研究

项目编号： No.61574002

项目类型： 面上项目

立项/批准年度： 2016

项目学科： 无线电电子学、电信技术

项目作者： 陈毅坚

作者单位： 北京大学

项目金额： 16万元

中文摘要： 光刻技术与工艺涨落所引发的器件/电路变动性是亚10纳米集成电路技术的核心难题。由于极紫外（EUV）光刻技术的研发滞后，以及光刻机对准精度的限制，业界开始采用自对准多重图案成形技术来制造电路中最困难的几个关键层。该技术采用了芯模和侧墙工艺，可大幅提高电路的密度和均匀性，但依赖于切孔（cuts）和导通孔（vias）来形成一维电路。切孔/导通孔的极小工艺窗口以及光刻对准精度有限将大幅降低这些关键层的光刻良率，是一个亟待解决的工艺难题。我们将研究不同类型的自对准光刻技术的复杂性和优缺点，探索具有大规模量产能力的工艺技术路线以及提高光刻良率的版图分解与合成办法。同时，我们将研究能突破传统的（基于表面电势的）晶体管模型的新办法，构建基于表面电场的新器件模型，以便把泊松方程的非线性和工艺涨落效应考虑进来。

中文关键词： 光刻；自对准多重图案成形技术；工艺变动性；多栅极晶体管；非线性泊松方程

英文摘要： Patterning technology and process variability pose tremendous challenges to sub-10nm IC technology. Due to the delay of EUV lithography and the overlay limitation of optical scanners, the semiconductor industry starts to research self-aligned multiple patterning (SAMP) techniques for the critical-layer patterning. Based on the mandrel and spacer engineering, SAMP techniques not only increase the feature density, but also improve the CD uniformity. However, current SAMP based patterning schemes heavily rely on cut/via patterning to form 1-D circuits. The extremely small process window of cut/via patterning process will significantly degrade the yield and this remains to be a challenging issue to be solved in the near future. We shall study process characteristics of various SAMP techniques, identify the optimal patterning solution, and develop efficient layout decomposition/synthesis algorithm to improve the process yield. Moreover, deep nano-scale process variability such as spatial fluctuation of dopant profiles and line-width roughness (LWR) trigger the need of an accurate model capable of predicting the behavior of multi-gate MOSFETs in the presence of process variability. We propose an analytic surface-field based compact model for multi-gate MOSFETs using the variable transformation method. This new modeli

英文关键词： Lithography；Self-aligned multiple patterning；Process variability；Multi-gate MOSFET；Nonlinear Poisson's equation