Targeting high-throughput and low-power communications, we implement two successive cancellation (SC) decoders for polar codes. With $16nm$ ASIC technology, the area efficiency and energy efficiency are $4Tbps/mm^2$ and $0.63pJ/bit$, respectively, for the unrolled decoder, and $561Gbps/mm^2$ and $1.21pJ/bit$, respectively, for the recursive decoder. To achieve such a high throughput, a novel code construction, coined as fast polar codes, is proposed and jointly optimized with a highly-parallel SC decoding architecture. First, we reuse existing modules to fast decode more outer code blocks, and then modify code construction to facilitate faster decoding for all outer code blocks up to a degree of parallelism of $16$. Furthermore, parallel comparison circuits and bit quantization schemes are customized for hardware implementation. Collectively, they contribute to an $2.66\times$ area efficiency improvement and $33\%$ energy saving over the state of the art.
翻译:以高通量和低功率通信为目标,我们连续两次取消极地代码的编码(SC)分解器。使用1,600万美元的ACIC技术,区域效率和能效分别为:无滚解码器4Tbps/mm ⁇ 2美元和0.63pJ/bit美元,再用561Gbps/mm ⁇ 2美元和1.21pJ/bit美元分别用于循环解码器。为了实现如此高的分解器,我们提出并联合优化了以快速极地代码生成的新型代码结构。首先,我们重新使用现有模块快速解码更多的外部代码块,然后修改代码结构,以便加快所有外部代码块的解码速度,使其达到16美元的平行度。此外,为硬件的实施定制了平行比较电路和小孔化计划。它们共同帮助了266美元地区效率的提高和33美元对艺术状态的节能。