To operate efficiently across a wide range of workloads with varying power requirements, a modern processor applies different current management mechanisms, which briefly throttle instruction execution while they adjust voltage and frequency to accommodate for power-hungry instructions (PHIs) in the instruction stream. Doing so 1) reduces the power consumption of non-PHI instructions in typical workloads and 2) optimizes system voltage regulators' cost and area for the common use case while limiting current consumption when executing PHIs. However, these mechanisms may compromise a system's confidentiality guarantees. In particular, we observe that multilevel side-effects of throttling mechanisms, due to PHI-related current management mechanisms, can be detected by two different software contexts (i.e., sender and receiver) running on 1) the same hardware thread, 2) co-located Simultaneous Multi-Threading (SMT) threads, and 3) different physical cores. Based on these new observations on current management mechanisms, we develop a new set of covert channels, IChannels, and demonstrate them in real modern Intel processors (which span more than 70% of the entire client and server processor market). Our analysis shows that IChannels provides more than 24x the channel capacity of state-of-the-art power management covert channels. We propose practical and effective mitigations to each covert channel in IChannels by leveraging the insights we gain through a rigorous characterization of real systems.
翻译:为了在不同的电力要求下高效率地处理各种工作量,现代处理器采用不同的现行管理机制,这些管理机制在调整电压和频率以适应指令流中的缺电指令时,会短暂地加速电压和频率,以适应指令流中的缺电指令;这样做1,在典型工作量中减少非PHI指令的耗电量;2,在使用PHI时优化系统调压调节器的成本和领域,同时限制目前的消费,但在执行PHI时,这些机制可能会损害系统的保密保障;特别是,我们观察到,由于PHI相关的当前管理机制,通过两种不同的软件环境(即发送器和接收器),可以检测到节流机制的多层次副作用,以适应在1个相同的硬件线上运行的电源和频率;2,共同放置SMT(SMT)多功能导线,以及3个不同的物理核心。根据对当前管理机制的这些新观察,我们开发了一套实际的隐性渠道,即Ihannels,并在实际的Intel处理器中展示这些备用机制的多重副作用(超过70 %的发送器的发送器),通过我们整个客户端端端端端端端端的系统提供整个的网络的网络的系统,从而显示整个客户端端端端端点的系统。