Analog In-Memory Computing (AIMC) is emerging as a disruptive paradigm for heterogeneous computing, potentially delivering orders of magnitude better peak performance and efficiency over traditional digital signal processing architectures on Matrix-Vector multiplication. However, to sustain this throughput in real-world applications, AIMC tiles must be supplied with data at very high bandwidth and low latency; this poses an unprecedented pressure on the on-chip communication infrastructure, which becomes the system's performance and efficiency bottleneck. In this context, the performance and plasticity of emerging on-chip wireless communication paradigms provide the required breakthrough to up-scale on-chip communication in large AIMC devices. This work presents a many-tile AIMC architecture with inter-tile wireless communication that integrates multiple heterogeneous computing clusters, embedding a mix of parallel RISC-V cores and AIMC tiles. We perform an extensive design space exploration of the proposed architecture and discuss the benefits of exploiting emerging on-chip communication technologies such as wireless transceivers in the millimeter-wave and terahertz bands.
翻译:模拟中计算(AIMC)正在成为多种计算的一种破坏性模式,在矩阵-变量乘法方面,可能比传统的数字信号处理结构产生更高的顶峰性能和效率,然而,为了维持真实世界应用中的这种吞吐量,AIMC平面必须提供非常高的带宽和低延缓度的数据;这对机上通信基础设施造成前所未有的压力,成为系统性能和效率瓶颈;在这方面,机上无线通信模式的性能和可塑性,为在大型机上安装无线通信设备,提供了升级机上通信所需的突破。 这项工作展示了多层的AIMC结构,包括多层混合计算组、同时混合的RISC-V核心和AIMC砖块。 我们对拟议的结构进行了广泛的设计空间探索,并讨论了利用诸如毫米波和千兆赫波中无线转发器等新型芯通信技术的好处。