Data protection is a severe constraint in the heterogeneous IoT era. This article presents a Hardware-Software Co-Simulation of AES-128 bit encryption and decryption for IoT Edge devices using the Xilinx System Generator (XSG). VHDL implementation of AES-128 bit algorithm is done with ECB and CTR mode using loop unrolled and FSM-based architecture. It is found that AES-CTR and FSM architecture performance is better than loop unrolled architecture with lesser power consumption and area. For performing the Hardware-Software Co-Simulation on Zedboard and Kintex-Ultra scale KCU105 Evaluation Platform, Xilinx Vivado 2016.2 and MATLAB 2015b is used. Hardware emulation is done for grey images successfully. To give a practical example of the usage of proposed framework, we have applied it for Biomedical Images (CTScan Image) as a case study. Security analysis in terms of the histogram, correlation, information entropy analysis, and keyspace analysis using exhaustive search and key sensitivity tests is also done to encrypt and decrypt images successfully.
翻译:该文章展示了使用 Xilinx 系统生成器(XSG)对 IoT Edge 设备进行 AES-128 位位加密和解密模拟的硬件-软件软件软件联合模拟。 VHDL 使用环状和基于密克罗尼西亚的架构,与欧洲央行和CTR 模式一起实施 AES-128 位算法。发现AES-CTR 和密克罗尼西亚结构的性能优于电耗和面积较少的循环无滚动结构。为在 Zedboard 和 Kintex-Ultra 级 KCU105 评估平台上进行硬件软件-软件共同模拟和解密, Xilinx Vivado 2016.2 和 MATLAB 2015b 使用。对灰色图像成功地进行了硬件模拟。为使用拟议框架的实用实例,我们将其应用于生物医学图像(CTScan 图像) 的案例研究。还成功地进行了其直图、相关性、信息加密分析和关键空间分析。