This paper presents GraphAGILE, a domain-specific FPGA-based overlay accelerator for graph neural network (GNN) inference. GraphAGILE consists of (1) \emph{a novel unified architecture design} with an \emph{instruction set}, and (2) \emph{a compiler} built upon the instruction set that can quickly generate optimized code. Due to the proposed instruction set architecture (ISA) and the compiler, GraphAGILE does not require any FPGA reconfiguration when performing inference on various GNN models and input graphs. For the architecture design, we propose a novel hardware module named Adaptive Computation Kernel (ACK), that can execute various computation kernels of GNNs, including general matrix multiplication (GEMM), sparse-dense matrix multiplication (SpDMM) and sampled dense-dense matrix multiplication (SDDMM). The compiler takes the specifications of a GNN model and the graph meta data (e.g., the number of vertices and edges) as input, and generates a sequence of instructions for inference execution. We develop the following compiler optimizations to reduce inference latency: (1) computation order optimization that automatically reorders the computation graph to reduce the total computation complexity, (2) layer fusion that merges adjacent layers to reduce data communication volume, (3) data partitioning with a partition-centric execution scheme that partitions the input graph to fit the available on-chip memory of FPGA, (4) kernel mapping that automatically selects execution mode for ACK, and performs task scheduling to overlap computation with data communication and achieves dynamic load balance. We implement GraphAGILE on a state-of-the-art FPGA platform, Xilinx Alveo U250. GraphAGILE can execute widely used GNN models, including GCN, GAT, GIN, GraphSAGE, SGC and other GNN models supported by GraphGym.
翻译:本文展示了基于图形神经网络( GNN) 的基于域的 FGGA 的超升加速器 GrapAGILE 。 用于图形神经网络( GNN ) 的推断。 GrapAGILE 包含 (1) \ emph{ a 新的统一建筑设计} 和 (2) \ emph{ a 编译器基于能够快速生成优化代码的教学集。 由于拟议的指令集架构( ISA) 和编译器, GrapAGILE 在对各种 GNN 模型和输入图形进行推断时不需要 FPGAGAGA 重叠。 对于建筑设计,我们提议了一个名为调制调制调制内核( AK) 的新硬件模块,这个模块可以执行 GNGNT 的计算内核增增量( GDMMM ) 和样本密度矩阵增量增量。 编译器将GNNNFI 的内存模型和平面元数据调数据转换为优化执行流程。