Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is crucial to develop tools that allow specific design space explorations. To this aim, in this paper we present a technique to perform a spatio-temporal characterization of quantum circuits running in multi-chip quantum computers. Specifically, we focus on the analysis of the qubit traffic resulting from operations that involve qubits residing in different cores, and hence quantum communication across chips, while also giving importance to the amount of intra-core operations that occur in between those communications. Using specific multi-core performance metrics and a complete set of benchmarks, our analysis showcases the opportunities that the proposed approach may provide to guide the design of multi-core quantum computers and their interconnects.
翻译:量子计算机可扩缩的终极解决办法是量子多处理器。根据在某种量子内联网上连接的中度量子(NISQ)芯片,这些芯片能够根据当前和近距离的未来技术实施大型算法。为了优化这些结构,开发能够进行具体设计空间探索的工具至关重要。为此,我们在本文件中介绍了对多芯量子计算机运行的量子电路进行瞬时定性的技术。具体地说,我们侧重于分析由于涉及不同核心的 ⁇ 的操作而导致的量子流量,从而也重视在芯片之间的量子通信,同时重视这些通信之间发生的核心内部业务数量。我们的分析利用具体的多核心性能指标和一整套基准,展示了拟议方法为指导多芯量子计算机的设计及其相互联系而可能提供的机会。