Memory disaggregation is being considered as a strong alternative to traditional architecture to deal with the memory under-utilization in data centers. Disaggregated memory can adapt to dynamically changing memory requirements for the data center applications like data analytics, big data, etc., that require in-memory processing. However, such systems can face high remote memory access latency due to the interconnect speeds. In this paper, we explore a rack-scale disaggregated memory architecture and discuss the various design aspects. We design a trace-driven simulator that combines an event-based interconnect and a cycle-accurate memory simulator to evaluate the performance of disaggregated memory system at the rack scale. Our study shows that not only the interconnect but the contention in the remote memory queues also adds significantly to remote memory access latency. We introduces a memory allocation policy to reduce the latency compared to the conventional policies. We conduct experiments using various benchmarks with diverse memory access patterns. Our study shows encouraging results towards the rack-scale memory disaggregation and acceptable average memory access latency.
翻译:解耦内存被认为是应对数据中心内存利用低的强有力的替代方案。解耦内存可以适应于需要内存处理的数据中心应用,例如数据分析,大数据等。然而,由于互连速度,这些系统可能面临高延迟的远程内存访问。在本文中,我们探讨了一种机架级解耦内存架构,并讨论了各种设计方面。我们设计了一个轨迹驱动模拟器,将基于事件的互连和一个循环精确的内存模拟器结合起来,以评估机架规模下解耦内存系统的性能。我们的研究表明,除了互连之外,远程内存队列的争用也显著增加了远程内存访问延迟。我们引入了一种内存分配策略,以减少延迟,相对于传统策略来说,我们的策略取得了显著的减少。我们使用各种具有不同内存访问模式的基准测试进行了实验。我们的研究向机架级内存解耦和可接受的平均内存访问延迟取得了令人鼓舞的结果。