On the Optimization of Behavioral Logic Locking for High-Level Synthesis

The globalization of the electronics supply chain requires effective methods to thwart reverse engineering and IP theft. Logic locking is a promising solution, but there are still several open concerns. First, even when applied at a higher level of abstraction, locking has significant overhead without improving the security metric. Second, optimizing a security metric is application-dependent and designers must evaluate and compare alternative solutions. We propose a framework to optimize the use of behavioral locking during the high-level synthesis (HLS) of IP cores. Our method operates on chip's specification (before HLS) and it is compatible with all HLS tools, complementing industrial EDA flows. The framework supports different meta-heuristics to explore the design space and to select points to lock automatically. Our method optimizes a given security metric better than topological locking: 1) we always identify a valid solution that optimizes the security metric; 2) we minimize the number of bits used for locking; and 3) we make a better use of hardware resources.