SOI基高迁移率双沟道材料制备研究

项目名称： SOI基高迁移率双沟道材料制备研究

项目编号： No.61274136

项目类型： 面上项目

立项/批准年度： 2013

项目学科： 无线电电子学、电信技术

项目作者： 张苗

作者单位： 中国科学院上海微系统与信息技术研究所

项目金额： 80万元

中文摘要： 应变硅技术通过在传统的体硅器件中引入应力增加载流子迁移率，从而提高CMOS 器件的性能，因而被认为是推动集成电路沿摩尔定律继续发展的核心技术之一。本项目针对应变硅空穴迁移率相对较低这一问题，提出将应变硅与空穴迁移率高的SiGe材料相结合，形成绝缘体上sSi-SiGe（sSi-SiGe-OI） 双沟道高迁移率新材料，可以用来在同一衬底上实现高电子迁移率的NMOS 以及高空穴迁移率的PMOS。 本项目目标研制成功6英寸sSi-SiGe-OI双沟道高迁移率晶圆片，深入研究Si/SiGe材料异质外延与氧化浓缩过程中缺陷演变以及应变维持与释放等得物理机制与规律，并探索双应变沟道材料在器件制备过程中的行为，研究应变材料特性对载流子迁移率的影响，优化材料关键参数，为特征线宽22 nm节点以下微纳电子时代提供高端硅基衬底材料。

中文关键词： 应变硅；锗硅；SOI；；

英文摘要： As strained Si (sSi) technology is able to improve the CMOS' performance by introducing stress into the conventional Si device to enhance the carrier mobility, strained Si technology is considered as one of the core technologies to support the development of IC industry along the Moore's law. However, compared to the electron mobility, the enhancement of the hole mobility in strained Si is limited and relatively insufficient. In this project, the researchers propose to fabricate a SOI structure with sSi-SiGe dual-channel material in which strained Si could provide high electron mobility, and SiGe could provide comparable hole mobility simultaneously. Therefore, NMOS with high electron mobility and PMOS with high hole mobility can be realized on one single substrate as proposed. The ultimate aim of this project is to achieve 6 inch SOI wafer with sSi-SiGe dual-channel material, and provide high-end substrates for future electronic devices in micro/nanoelectronic era as the process technology is approaching the 22nm logic node. The project will focus on the following three aspects to carry out scientific researches: (1) Systematically investigating the physical mechanism underlying dislocations evolution and stress relaxation during Si/SiGe heterostructure epitaxial growth and oxidation-condensation process. (2

英文关键词： strain si；SiGe；SOI；；